1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device of common I/O type using I/O lines for reading and writing data in common.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory), one of the typical semiconductor memory devices, is utilized in a variety of systems as a storage device suitable for a high integration and a mass storage in a semiconductor device.
Data writing in a DRAM is generally performed in the following four operations. The first is a sense operation in which a slight voltage difference appearing at a pair of bit lines in accordance with data stored in a memory cell is amplified by a sense amplifier to a great extent. The second is a write operation in which a pair of bit lines connected to a memory cell to which data is to be written are connected to a pair of I/O lines and write data on the pair of I/O lines is written to the pair of bit lines. The third is a restore operation in which storage data of a non-selected cell once corrupted in response to activation of a word line and the above written data are written back to an original memory cell. The fourth is an equalize operation in which potentials of the pair of bit lines are initialized. Data writing is performed by a series of the above four operations. The series of operations is generally referred to as a “Read modify Write operation.”
In this “Read modify Write operation,” after the sense amplifier is activated in response to receiving a sense amplifier activation signal and the slight voltage difference on the pair of bit lines is amplified to a sufficiently large voltage difference by the sense amplifier, a column selection signal is activated and the pair of bit lines are electrically connected to the pair of I/O lines, whereby data is written from the pair of I/O lines to the pair of bit lines.
In contrast, a “Write before Sense operation” is also known in which a column selection signal is activated without waiting for a voltage amplification by a sense amplifier so that a high-speed operation is realized. As a circuit configuration realizing this “Write before Sense operation,” a DRAM of separate I/O type is generally known in which pairs of I/O lines for reading and writing data are separately provided. In this separate I/O type DRAM, the column selection signal can be activated at the same time as or before activation of the sense amplifier activation signal. Accordingly, the above-described sense operation and write operation can be performed at the same time. Therefore, an operation of the separate I/O type DRAM employing the “Write before Sense operation” is faster than that of the common I/O type DRAM employing the “Read modify Write operation.”
In the separate I/O type DRAM, however, a pair of bit lines are connected to pairs of I/O lines for reading data and for writing data. Therefore, two connection gates are required for each pair of bit lines. Accordingly, a problem arises that elements required for the separate I/O type DRAM are greater in number than those required for the common I/O type DRAM. A further problem is that a circuit area of the separate I/O type DRAM is larger than that of the common I/O type DRAM.
To address the above problems, Japanese Patent Laying-Open No. 6-60657 discloses the following DRAM. In this DRAM, a configuration of I/O lines is of an I/O common type. In a connection gate circuit connecting a pair of bit lines to a pair of I/O lines, a separate I/O type circuit configuration is employed for data reading, while for data writing a gate transistor receiving a write control signal at its gate is provided between a gate transistor for reading data and the pair of bit lines. This enables a decrease in number of pair of I/O lines and elements, downsizing of a chip, and a cost reduction while taking advantage of the characteristic of the separate I/O type DRAM.
Through employment of a separate I/O type circuit configuration for achieving a high-speed operation of a DRAM, a circuit area is increased as described above. In contrast, a conventional common I/O type DRAM can reduce a circuit area in comparison with the separate I/O type DRAM. The common I/O type DRAM, however, cannot realize the “Write before Sense operation.” In the following, description will be given about a problem that arises when the “Write before Sense operation” is performed in the conventional common I/O type DRAM.
If a column selection signal is activated before activation of a sense amplifier activation signal in data writing in the common I/O type DRAM, voltages of a pair of bit lines connected to a pair of I/O lines (also referred to as a “pair of selected bit lines” hereinafter) swing to the full extent. As a result, a bit line adjacent to the pair of selected bit lines may suffer coupling due to the full voltage swing at the pair of selected bit lines, and the DRAM may fail to operate properly.
That is, when a word line is activated, data stored in memory cells connected to the word line is read on a corresponding pair of bit lines as a slight voltage change, regardless of whether or not the memory cell is selected. When the pair of selected bit lines is connected to the pair of I/O lines prior to the activation of the sense amplifier and a voltage of the pair of selected bit lines changes in accordance with a voltage appearing at the pair of I/O lines in accordance with write data, a voltage of an adjacent bit line that has not yet been amplified by the sense amplifier is affected by coupling from the pair of selected bit lines. As a result, a content of storage data of the adjacent bit line affected by the coupling may be inverted.
The DRAM disclosed in Japanese Patent Laying-Open No. 6-60657 described above takes advantage of the characteristic of the separate I/O type DRAM, and also employs the common I/O type circuit configuration, thereby enabling a reduction in circuit area. In writing data, however, the column selection signal and the write control signal are not activated before the sense amplifier is activated and the voltage on the pair of bit lines is sufficiently amplified. If the column selection signal and the write control signal are activated before the activation of the sense amplifier, a problem of the above-described coupling arises. In other words, the “Write before Sense operation” can not be realized in this DRAM.